CPU_CYCLESINSTRUCTIONSCACHE_REFERENCESCACHE_MISSESBRANCH_INSTRUCTIONSBRANCH_MISSESBUS_CYCLESSTALLED_CYCLES_FRONTENDSTALLED_CYCLES_BACKENDREF_CPU_CYCLESMAXpub const HW = enum(u32) {
CPU_CYCLES,
INSTRUCTIONS,
CACHE_REFERENCES,
CACHE_MISSES,
BRANCH_INSTRUCTIONS,
BRANCH_MISSES,
BUS_CYCLES,
STALLED_CYCLES_FRONTEND,
STALLED_CYCLES_BACKEND,
REF_CPU_CYCLES,
MAX,
pub const CACHE = enum(u32) {
L1D,
L1I,
LL,
DTLB,
ITLB,
BPU,
NODE,
MAX,
pub const OP = enum(u32) {
READ,
WRITE,
PREFETCH,
MAX,
};
pub const RESULT = enum(u32) {
ACCESS,
MISS,
MAX,
};
};
}