pub const cpu = struct {
    pub const baseline_rv32: CpuModel = .{
        .name = "baseline_rv32",
        .llvm_name = null,
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .d,
            .i,
            .m,
        }),
    };
    pub const baseline_rv64: CpuModel = .{
        .name = "baseline_rv64",
        .llvm_name = null,
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
        }),
    };
    pub const generic: CpuModel = .{
        .name = "generic",
        .llvm_name = "generic",
        .features = featureSet(&[_]Feature{}),
    };
    pub const generic_rv32: CpuModel = .{
        .name = "generic_rv32",
        .llvm_name = "generic-rv32",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .i,
        }),
    };
    pub const generic_rv64: CpuModel = .{
        .name = "generic_rv64",
        .llvm_name = "generic-rv64",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .i,
        }),
    };
    pub const rocket: CpuModel = .{
        .name = "rocket",
        .llvm_name = "rocket",
        .features = featureSet(&[_]Feature{}),
    };
    pub const rocket_rv32: CpuModel = .{
        .name = "rocket_rv32",
        .llvm_name = "rocket-rv32",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .i,
            .zicsr,
            .zifencei,
        }),
    };
    pub const rocket_rv64: CpuModel = .{
        .name = "rocket_rv64",
        .llvm_name = "rocket-rv64",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .i,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_7_series: CpuModel = .{
        .name = "sifive_7_series",
        .llvm_name = "sifive-7-series",
        .features = featureSet(&[_]Feature{
            .no_default_unroll,
            .short_forward_branch_opt,
            .use_postra_scheduler,
        }),
    };
    pub const sifive_e20: CpuModel = .{
        .name = "sifive_e20",
        .llvm_name = "sifive-e20",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_e21: CpuModel = .{
        .name = "sifive_e21",
        .llvm_name = "sifive-e21",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_e24: CpuModel = .{
        .name = "sifive_e24",
        .llvm_name = "sifive-e24",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .f,
            .i,
            .m,
            .zifencei,
        }),
    };
    pub const sifive_e31: CpuModel = .{
        .name = "sifive_e31",
        .llvm_name = "sifive-e31",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_e34: CpuModel = .{
        .name = "sifive_e34",
        .llvm_name = "sifive-e34",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .f,
            .i,
            .m,
            .zifencei,
        }),
    };
    pub const sifive_e76: CpuModel = .{
        .name = "sifive_e76",
        .llvm_name = "sifive-e76",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .a,
            .c,
            .f,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_opt,
            .use_postra_scheduler,
            .zifencei,
        }),
    };
    pub const sifive_p450: CpuModel = .{
        .name = "sifive_p450",
        .llvm_name = "sifive-p450",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .auipc_addi_fusion,
            .c,
            .conditional_cmv_fusion,
            .d,
            .i,
            .lui_addi_fusion,
            .m,
            .no_default_unroll,
            .unaligned_scalar_mem,
            .unaligned_vector_mem,
            .use_postra_scheduler,
            .za64rs,
            .zba,
            .zbb,
            .zbs,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
        }),
    };
    pub const sifive_p670: CpuModel = .{
        .name = "sifive_p670",
        .llvm_name = "sifive-p670",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .auipc_addi_fusion,
            .c,
            .conditional_cmv_fusion,
            .i,
            .lui_addi_fusion,
            .m,
            .no_default_unroll,
            .no_sink_splat_operands,
            .unaligned_scalar_mem,
            .unaligned_vector_mem,
            .use_postra_scheduler,
            .v,
            .za64rs,
            .zba,
            .zbb,
            .zbs,
            .zfhmin,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zifencei,
            .zihintntl,
            .zihintpause,
            .zihpm,
            .zvbb,
            .zvknc,
            .zvkng,
            .zvksc,
            .zvksg,
        }),
    };
    pub const sifive_s21: CpuModel = .{
        .name = "sifive_s21",
        .llvm_name = "sifive-s21",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_s51: CpuModel = .{
        .name = "sifive_s51",
        .llvm_name = "sifive-s51",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .i,
            .m,
            .zicsr,
            .zifencei,
        }),
    };
    pub const sifive_s54: CpuModel = .{
        .name = "sifive_s54",
        .llvm_name = "sifive-s54",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .zifencei,
        }),
    };
    pub const sifive_s76: CpuModel = .{
        .name = "sifive_s76",
        .llvm_name = "sifive-s76",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_opt,
            .use_postra_scheduler,
            .zifencei,
            .zihintpause,
        }),
    };
    pub const sifive_u54: CpuModel = .{
        .name = "sifive_u54",
        .llvm_name = "sifive-u54",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .zifencei,
        }),
    };
    pub const sifive_u74: CpuModel = .{
        .name = "sifive_u74",
        .llvm_name = "sifive-u74",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .short_forward_branch_opt,
            .use_postra_scheduler,
            .zifencei,
        }),
    };
    pub const sifive_x280: CpuModel = .{
        .name = "sifive_x280",
        .llvm_name = "sifive-x280",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .dlen_factor_2,
            .i,
            .m,
            .no_default_unroll,
            .optimized_zero_stride_load,
            .short_forward_branch_opt,
            .use_postra_scheduler,
            .v,
            .zba,
            .zbb,
            .zfh,
            .zifencei,
            .zvfh,
            .zvl512b,
        }),
    };
    pub const spacemit_x60: CpuModel = .{
        .name = "spacemit_x60",
        .llvm_name = "spacemit-x60",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .dlen_factor_2,
            .i,
            .m,
            .ssccptr,
            .sscofpmf,
            .sscounterenw,
            .sstc,
            .sstvala,
            .sstvecd,
            .svade,
            .svbare,
            .svinval,
            .svnapot,
            .svpbmt,
            .v,
            .za64rs,
            .zba,
            .zbb,
            .zbc,
            .zbkc,
            .zbs,
            .zfh,
            .zic64b,
            .zicbom,
            .zicbop,
            .zicboz,
            .ziccamoa,
            .ziccif,
            .zicclsm,
            .ziccrse,
            .zicntr,
            .zicond,
            .zifencei,
            .zihintpause,
            .zihpm,
            .zkt,
            .zvfh,
            .zvkt,
            .zvl256b,
        }),
    };
    pub const syntacore_scr1_base: CpuModel = .{
        .name = "syntacore_scr1_base",
        .llvm_name = "syntacore-scr1-base",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .i,
            .no_default_unroll,
            .zicsr,
            .zifencei,
        }),
    };
    pub const syntacore_scr1_max: CpuModel = .{
        .name = "syntacore_scr1_max",
        .llvm_name = "syntacore-scr1-max",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .i,
            .m,
            .no_default_unroll,
            .zicsr,
            .zifencei,
        }),
    };
    pub const syntacore_scr3_rv32: CpuModel = .{
        .name = "syntacore_scr3_rv32",
        .llvm_name = "syntacore-scr3-rv32",
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .c,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zicsr,
            .zifencei,
        }),
    };
    pub const syntacore_scr3_rv64: CpuModel = .{
        .name = "syntacore_scr3_rv64",
        .llvm_name = "syntacore-scr3-rv64",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .i,
            .m,
            .no_default_unroll,
            .use_postra_scheduler,
            .zicsr,
            .zifencei,
        }),
    };
    pub const veyron_v1: CpuModel = .{
        .name = "veyron_v1",
        .llvm_name = "veyron-v1",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .auipc_addi_fusion,
            .c,
            .d,
            .i,
            .ld_add_fusion,
            .lui_addi_fusion,
            .m,
            .shifted_zextw_fusion,
            .ventana_veyron,
            .xventanacondops,
            .zba,
            .zbb,
            .zbc,
            .zbs,
            .zexth_fusion,
            .zextw_fusion,
            .zicbom,
            .zicbop,
            .zicboz,
            .zicntr,
            .zifencei,
            .zihintpause,
            .zihpm,
        }),
    };
    pub const xiangshan_nanhu: CpuModel = .{
        .name = "xiangshan_nanhu",
        .llvm_name = "xiangshan-nanhu",
        .features = featureSet(&[_]Feature{
            .@"64bit",
            .a,
            .c,
            .d,
            .i,
            .m,
            .no_default_unroll,
            .shifted_zextw_fusion,
            .svinval,
            .zba,
            .zbb,
            .zbc,
            .zbs,
            .zexth_fusion,
            .zextw_fusion,
            .zicbom,
            .zicboz,
            .zifencei,
            .zkn,
            .zksed,
            .zksh,
        }),
    };
}